Reuse issues on the verification of embedded MCU cores

Author

Sabbatini, Narcizo, Jr. ; Brochi, Antonio Mauricio ; Nunes, Tulio Ibanez

Author_Institution

Motorola Semicond. Products Sector, Jaguariuna, Brazil

fYear

2002

fDate

6/24/1905 12:00:00 AM

Abstract

The main issues related to the verification of cores embedded in a microcontroller unit (MCU) are addressed in this paper. Issues such as verification environment design, simulation pattern strategies and reuse, as well as standalone and chip level verification are discussed. An analysis of the verification environment is performed from the perspective of the reuse across the design cycle, focussing on the core standalone and on the chip level verification. A case study analysis is included.

Keywords

circuit simulation; embedded systems; formal verification; industrial property; integrated circuit design; integrated circuit testing; logic simulation; microcontrollers; case study analysis; chip level verification; core reuse; design cycle reuse; embedded MCU core verification; microcontroller units; simulation pattern strategies; standalone verification; verification environment design; Central Processing Unit; Data processing; Energy consumption; Hardware; Memory management; Microcontrollers; Monitoring; Packaging; Performance analysis; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems, 2002. Proceedings of the Fourth IEEE International Caracas Conference on

Print_ISBN

0-7803-7380-4

Type

conf

DOI

10.1109/ICCDCS.2002.1004000

Filename

1004000