Title :
New three dimensional (3D) memory array architecture for future ultra high density DRAM (invited)
Author :
Masuoka, Fujio ; Endoh, Tetsuo ; Sakuraba, Hiroshi
Author_Institution :
Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan
fDate :
6/24/1905 12:00:00 AM
Abstract :
Three dimensional (3D) memory array architecture is realized by stacking several cells in series vertically up on each cell which is located in a two dimensional (2D) array matrix. Total bit-line capacitance of this proposed architecture´s DRAM is suppressed to 37% of that of a normal DRAM, when one bit-line has 1K-bit cells and the same design rules are used. Moreover, array area of a 1 Mbit DRAM using the proposed architecture, is reduced to 11.5% of that of a normal DRAM using the same design rules.
Keywords :
DRAM chips; capacitance; integrated circuit layout; memory architecture; 1 Mbit; 2D array matrix; 3D memory array architecture; DRAM architecture; DRAM array area; bit-line cells; design rules; total bit-line capacitance; ultra high density DRAM; vertically stacked cells; Capacitance; Capacitors; Decoding; Equivalent circuits; Joining processes; Memory architecture; Random access memory; Registers; Signal restoration; Stacking;
Conference_Titel :
Devices, Circuits and Systems, 2002. Proceedings of the Fourth IEEE International Caracas Conference on
Print_ISBN :
0-7803-7380-4
DOI :
10.1109/ICCDCS.2002.1004003
