Pipelining for speed doubling in MDFE

The data rate in decision feedback detectors is often limited by the time it takes the slicer to make a decision, followed by generating an output value from the decision feedback filter and finally establishing the input of the slicer for the next symbol period. It is shown that the equalized dibit response for multi-level decision feedback equalization can be designed so that the first tap of the feedback filter is 0, thereby allowing the operations of the critical path to be spread over 2 symbol periods. By eliminating the first coefficient of the feedback filter, an architecture which doubles the overall symbol rate by using 2 decision feedback detectors each operating at one-half the symbol rate is realizable. Architectural considerations for determining the error required in the LMS adaptation of the timing, gain and feedback equalizer are described