Low-power low-noise CMOS chopper amplifier

Author

Yang, Xiao ; Yang, Jing ; Lin, Li-fen ; Ling, Chao-dong

Author_Institution

Coll. of Inf. Sci. & Eng., Huaqiao Univ., Xiamen, China

fYear

2010

Firstpage

83

Lastpage

84

Abstract

Chopping technique is an efficient approach to decrease the low-frequency offset and 1/f noise of amplifiers. In this paper, a low-power low-noise CMOS chopper amplifier is designed. This chopper amplifier is composed of a two-stage amplifier. The high output impedance of the first stage and the equivalent Miller capacitance of the second stage amplifier constitute together a low pass filter to filter out the modulation noise, so the chopper amplifier need not the post low-pass filter, which can reduce the power consumption. The circuit of the presented chopper amplifier is designed and simulated with TSMC 0.18μm CMOS process and a 1.8V supply. Simulation results show that the equivalent input noise is 39nV/√Hz at 100 Hz and the power consumption is 117μW.

Keywords

CMOS analogue integrated circuits; low noise amplifiers; low-pass filters; low-power electronics; 1-f noise; TSMC CMOS process; equivalent Miller capacitance; frequency 100 Hz; low pass filter; low-frequency offset; low-power low-noise CMOS chopper amplifier; power 117 muW; size 0.18 mum; two-stage amplifier; voltage 1.8 V; CMOS integrated circuits; Capacitance; Choppers; Frequency modulation; Low pass filters; Noise; Power harmonic filters; Chopper amplifier; equivalent input noise; low-noise; low-pass filter;

fLanguage

English

Publisher

ieee

Conference_Titel

Anti-Counterfeiting Security and Identification in Communication (ASID), 2010 International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-6731-0

Type

conf

DOI

10.1109/ICASID.2010.5551831

Filename

5551831