High-speed comparator used for high-speed, high-resolution A/D converter

Author

Huang, Xingfa ; Li, Liang ; Zhang, Zhengping ; Chen, Liang ; Yu, Jinshan

Author_Institution

Nat. Labs. of Analog Integrated Circuits, Chongqing, China

fYear

2010

Firstpage

67

Lastpage

70

Abstract

Based on the application of high-speed, high-resolution A/D converter, this paper describes the design and implementation of a novel high-speed comparator. The comparator uses the high-speed, transmission delay stability technology, the auto-zero technology, and the cascade technology in order for the comparator to have the high-speed, high-resolution, transmission delay stability features. Its performances are verified by a 14-bit 125MSPS pipelined A/D converter which is developed in 0.35 μm CMOS-based process technology. The SFDR of the A/D converter is up to 87 dB at an input clock of 125 MHz with an input signal of 10 MHz.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; comparators (circuits); CMOS-based process technology; autozero technology; cascade technology; clock; frequency 10 MHz; frequency 125 MHz; high-speed comparator; high-speed high-resolution A/D converter; pipelined A/D converter; size 0.35 mum; transmission delay stability technology; word length 14 bit; Capacitors; Clocks; Converters; Delay; Latches; Preamplifiers; Switches; A/D converter; Comparator; high speed;

fLanguage

English

Publisher

ieee

Conference_Titel

Anti-Counterfeiting Security and Identification in Communication (ASID), 2010 International Conference on

Conference_Location

Chengdu

Print_ISBN

978-1-4244-6731-0

Type

conf

DOI

10.1109/ICASID.2010.5551835

Filename

5551835