Temporal parallel gate-level timing simulation

This paper introduces a radically different approach to parallel simulation for gate level design, aimed at completely eliminating the communication and synchronization overhead between simulators. It is based on a new concept of temporal parallel simulation: in contrast to traditional, spatially-distributed simulation, which partitions the design into multiple modules to be simulated concurrently, the proposed temporal parallel simulation partitions the single simulation run into multiple simulation runs in temporal domain. Experimental results demonstrate that linear speedup is possible for large designs and long simulation runs.