T-gate technology for N-polar GaN-based self-aligned MIS-HEMTs with state-of-the-art fMAX of 127 GHz: Pathway towards scaling to 30nm GaN HEMTs

In this paper, we demonstrate a self-aligned gate-first process for fabrication of T-gates without much degradation of fτ. The device layer structure is shown. The fabrication process involves formation of W/Cr gates using a self-aligned gate-etch process similar to the InGaAs MOSFET technology reported by Rodwell et. al. [2008, 2009]. After formation of a 130 nm long gates, graded InGaN/InN-based access regions are regrown by plasma MBE, followed by self-aligned T-gate formation. The process involves spin-coating the sample with thick layer of e-beam resist PMMA (~1μm) followed by height-selective etching of the resist to leave the resist everywhere except the top of the gate fingers. Any InGaN regrown on top and protective SiO₂ layer is then lifted off in hydro-fluoric acid. Ebeam lithography of 300 nm long top is done followed by deposition of Ti/Au. The schematic of the T-gate process is shown.