Title :
An image processing platform: RASH-IP
Author :
Asami, H. ; Yamagishi, Y. ; Imai, T. ; Takimoto, T. ; Amano, K. ; Nakagawa, M.
Author_Institution :
Mitsubishi Electr. Corp., Kanagawa, Japan
Abstract :
We developed an image processing platform RASH-IP on the basis of development know-how of FPGA-based parallel machine RASH. RASH-IP contains six ALTERA Stratix (EP1S25) FPGAs on the VME board. RASH-IP boards have 10 buses in order to transfer HDTV video image data with several FPGAs. Each FPGA is directly connected to an 8M-byte synchronous SRAM so that it can hold the large amount of data. Moreover, RASH-IP boards have parallel IO ports and serial IO ports for image data transmission between boards. We examined an application of affine-transfer processing of video image data on RASH-IP.
Keywords :
SRAM chips; field programmable gate arrays; parallel machines; reconfigurable architectures; system buses; video signal processing; ALTERA Stratix; EP1S25 FPGA; FPGA-based parallel machine RASH; HDTV video image; RASH-IP boards; VME board; image data transmission; image processing; parallel IO ports; parallel processing; reconfigurable computing; serial IO ports; synchronous SRAM;
Conference_Titel :
SICE 2004 Annual Conference
Conference_Location :
Sapporo
Print_ISBN :
4-907764-22-7
