Image filtering using partially and dynamically reconfiguration

Author

Yang, Huaqiu ; Zhang, Fanjiong ; Lai, Jinmei ; Wang, Yan

Author_Institution

ASIC & Syst. State Key Lab., Fudan Univ., Shanghai, China

fYear

2010

Firstpage

2067

Lastpage

2073

Abstract

Modular based partially and dynamically reconfigurable (PDR) FPGA system is an ideal solution for run-time image processing system which needs to change the function of the processing unit dynamically. Here we present a new PDR image filter based on our self-developed FDP FPGA Device. In this system, the transition bus (TB) structure is proposed for physical separation of the static/dynamic blocks as required in PDR system. And we demo the system with an image filter aimed at filtering out mix-noise. The experiment results show that the proposed PDR system meets the requirement of the run-time image filter by its flexibility, fast reconfiguration speed, and saving of logic resource.

Keywords

field programmable gate arrays; filtering theory; image processing; field programmable gate array; image filtering; logic resource; modular based dynamically reconfigurable; modular based partially reconfigurable; run-time image processing system; self-developed FDP FPGA device; static-dynamic blocks; transition bus structure; Field programmable gate arrays; Filtering; Filtering algorithms; Image processing; Noise; Pixel; Random access memory; FDP FPGA Device; partially and dynamically reconfigurable system; run-time image filter; transition bus structure;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5797-7

Type

conf

DOI

10.1109/ICSICT.2010.5667280

Filename

5667280