Floating-point nonlinear DSP coprocessor cell-two cycle chip

Implementation of systolic arrays has been hindered in the past due to a lack of building blocks, or cells. This paper presents a high-speed floating-point DSP coprocessor cell for rapid computation of elementary functions. Several nonlinear functions are typically needed in systolic arrays for signal and image processing algorithms, while the development costs as well as interconnection considerations warrant the use of only a few types of cells. With our approach all of the elementary functions needed can be incorporated on a single cell. Furthermore, a new result is produced every two clock cycles in a pipeline mode. The underlying principle which has made the combined goals of high-speed and multi-functionality possible, is significance-based second order interpolation of very small ROM tables. A 32 bit two-cycle chip for computing the square-root, fabricated in 2.0 micron CMOS technology, is presented. As an application example, a parallel architecture for CT image reconstruction for a Fan Beam CT System is briefly discussed