Analysis and measurement of a novel on-chip variable delay transmission line with fixed characteristic impedance

RF designs such as phased array antenna systems make use of on-chip electronically controllable delay elements. This paper presents simulations and measurements of on-chip variable delay transmission lines with fixed characteristic impedance in two different technologies. EM simulations in a 130 nm BiCMOS technology show a delay change of 15.6% is possible while the characteristic impedance of the novel transmission line varies a maximum of 3.7% from the 50 ¿ target between two possible delay states. Measurement results from a 45 nm SOI digital technology reveal a maximum delay change of 16.0% and a maximum characteristic impedance deviation between delay states of 7.4% in a 10 GHz region of the Ka-band between 25 GHz and 35 GHz.