Novel test structures for the characterization of latch-up tolerance in a bipolar and MOSFET merged device

A novel test structure was used to evaluate a latchup phenomenon in a bipolar and MOSFET merged device for the BiNMOS gate. Its characteristics were analyzed by varying the test pattern. In the latchup measurement, a MOS current was used to trigger the device, with setting the normal n-p-n bipolar transistor active. As a result, it was revealed that this parasitic phenomenon is associated with a parasitic bipolar transistor below the MOSFET gate, and it was verified that the parasitic collector resistance is the main cause of the parasitic bipolar turn on. In addition, a longer-channel MOSFET is helpful but not sufficient to form a latchup-free state. Consequently, it was confirmed that the test structures and measurement method provide an experimental basis for the latchup-free state