Reliability analysis of a new vertical MOSFET with bMPI structure for 1T-DRAM applications

Author

Chen, Cheng-Hsin ; Lin, Jyi-Tsong ; Lin, Po-Hsieh ; Eng, Yi-Chuen ; Chiu, Hsien-Nan ; Chang, Tzu-Feng ; Chen, Hsuan-Hsu

Author_Institution

Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan

fYear

2010

Firstpage

1692

Lastpage

1694

Abstract

We present a reliability analysis of a new vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM applications. The proposed 1T-DRAM device can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved by about 95% when compared to the planer bMPI 1T-DRAM. Owing to the double-gate structure, vertical bMPI has great gate controllability over the channel region; hence, it can reduce the short-channel effects (SCEs) and enhance the current drive. And the VbMPI 1T-DRAM cell can keep holes in nature body region, which leads to an increase in data retention time.

Keywords

DRAM chips; MOSFET; reliability; semiconductor device reliability; 1T-DRAM applications; MOSFET; bMPI Structure; block oxide structure; data retention time; pseudo-neutral region; reliability analysis; short-channel effects; Controllability; Fabrication; Logic gates; Programming; Temperature; Temperature sensors; Transient analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5797-7

Type

conf

DOI

10.1109/ICSICT.2010.5667297

Filename

5667297