Digitally intensive wireless transmitter architecture employing RF pulse width modulation

Author

Hyejeong Song ; Gharpurey, Ranjit

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA

fYear

2014

fDate

12-13 Oct. 2014

Firstpage

1

Lastpage

4

Abstract

A digitally-intensive Cartesian RF transmitter based on three-level pulse width modulation (PWM) is proposed. The architecture utilizes two PLL-based RF-PWM generators to modulate baseband I and Q signals to switching signals at RF, which are used to drive class-D output stages. Due to the use of a ring voltage controlled oscillator (VCO), the architecture is well-suited for multiband operation. A switched capacitor technique is used to provide a differential three-level RF-PWM output. The proposed transmitter is simulated in a 65-nm CMOS process, and achieves a peak output power of 22 dBm with 48% and 33% peak power added efficiency (PAE) at 900 MHz and 1.95 GHz respectively.

Keywords

CMOS integrated circuits; pulse width modulation; radio transmitters; switched capacitor networks; voltage-controlled oscillators; CMOS process; PLL-based RF-PWM generators; RF pulse width modulation; VCO; baseband I signals; baseband Q signals; differential three-level RF-PWM output; digitally intensive wireless transmitter architecture; digitally-intensive Cartesian RF transmitter; frequency 1.95 GHz; frequency 900 GHz; multiband operation; power added efficiency; ring voltage controlled oscillator; size 65 nm; three-level pulse width modulation; Baseband; Generators; Pulse width modulation; Radio frequency; Switches; Transmitters; CMOS power amplifier; Cartesian transmitter; PLL; class-D; pulse-width modulation (PWM); switched capacitor power amplifier; wireless;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems Conference (DCAS), 2014 IEEE Dallas

Conference_Location

Richardson, TX

Type

conf

DOI

10.1109/DCAS.2014.6965346

Filename

6965346