Title :
A 11-mW quadrature frequency tripler with fundamental cancellation
Author :
Tsai, Chien-Chung ; Chang, Derric ; Chen, Huan-Sheng ; Kuo, Chien-Nan
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
A low-power quadrature frequency tripler is designed by using the sub-harmonic mixer configuration. The circuit is implemented in CMOS 0.180 um technology. The frequency tripler consumes 11.5 mW, while the output buffers consumes 43.1 mW, all with supply voltage of 1.8 V. The fundamental Harmonic Rejection Ratio (HRR1) achieves more than 35 dB, and the conversion gain achieves -4.2 dB at output frequency of 4.5 GHz. The entire chip area occupied 1.4 × 1.1 mm2.
Keywords :
CMOS integrated circuits; frequency multipliers; mixers (circuits); CMOS technology; frequency 4.5 GHz; fundamental cancellation; harmonic rejection ratio; low-power quadrature frequency tripler; power 11 mW; power 43.1 mW; size 0.180 mum; subharmonic mixer configuration; CMOS technology; Circuits; Design engineering; Energy consumption; Filtering; Frequency conversion; Mixers; Power harmonic filters; Signal generators; Voltage; doubler; frequency tripler; harmonic rejection ratio; sub-harmonic mixer;
Conference_Titel :
Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2010 Topical Meeting on
Conference_Location :
New Orleans, LA
Print_ISBN :
978-1-4244-5456-3
DOI :
10.1109/SMIC.2010.5422967
