A hot carrier parallel testing technique to give a reliable extrapolation

A technique for wafer level parallel testing of hot-carrier lifetime has been developed. Transistors of the same dimensions were adjacently arranged on the same chip, and the lifetimes were extrapolated from their measured lifetime at a low drain voltage for practical use. This technique was applied to the optimization of LDD (lightly doped drain) sidewall thickness. This technique eliminates the disturbance of the hot-carrier lifetime extrapolation caused by nonuniformity of the hot-carrier lifetimes on a wafer, and makes possible optimization of process parameters in a short period of time