Timing optimization for deep sub-micron hierarchical design

In this paper, we use design planning method to partition a flat design based on SAED 90 nm process technology into blocks and created interface logic models (ILMs) for each blocks. Using the hierarchical design including ILM, the runtime of the place optimization stage, clock optimization stage and route optimization stage is reduced to 28.8%, 27.7% and 43% relatively, meanwhile the boundary timing become more optimal which can also prove the timing accuracy of ILM.