DocumentCode
1628448
Title
Data frame synchronization sequence processor in HiNoC receiver
Author
Cui, Xiaoxin
Author_Institution
Inst. of Microelectron., Peking Univ., Beijing, China
fYear
2010
Firstpage
602
Lastpage
604
Abstract
A data frame synchronization sequence processor in HiNoC receiver is implemented in this paper. It is the important module for channel estimation and channel correction. 63-point FFT, phase extracting method and so on are presented considering hardware resource. The design has been fabricated with SMIC 0.13um technology.
Keywords
UHF integrated circuits; channel estimation; fast Fourier transforms; microprocessor chips; network-on-chip; radio transceivers; synchronisation; FFT; HiNoC receiver; SMIC technology; channel correction; channel estimation; data frame synchronization sequence processor; phase extracting method; size 0.13 mum; Channel estimation; Discrete Fourier transforms; Hardware; Modulation; Synchronization; Table lookup; Transceivers;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location
Shanghai
Print_ISBN
978-1-4244-5797-7
Type
conf
DOI
10.1109/ICSICT.2010.5667314
Filename
5667314
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