A CMOS current-mode pipeline ADC using zero-voltage sampling technique

Author

Hui, Ronny C C ; Luong, Howard C.

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, Hong Kong

Volume

1

fYear

1998

Firstpage

9

Abstract

A low-voltage low-power CMOS current-mode pipeline ADC is presented. Zero-voltage sampling technique and regulated cascode circuits are combined in the sample-and-hold circuits to increase the resolution. Dynamic latched-type comparators are used to implement high-speed low-power sub-ADCs. The multiplying DAC and the comparators are used with a digital error correction (DEC) circuit to realize a low-voltage low-power current-mode pipeline ADC. Simulation shows that the ADC can work at 20 MHz with an 8-bit resolution. The power consumption is 22 mW

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); error correction; pipeline processing; sample and hold circuits; 20 MHz; 22 mW; 8 bit; CMOS; current-mode pipeline ADC; digital error correction; dynamic latched-type comparators; low-power sub-ADCs; multiplying DAC; power consumption; regulated cascode circuits; resolution; sample-and-hold circuits; zero-voltage sampling technique; CMOS technology; Capacitors; Circuits; Energy consumption; Error correction; Error correction codes; Pipelines; Sampling methods; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.704122

Filename

704122