Title :
A 10-bit 1MS/s low power SAR ADC for RSSI application
Author :
Zeng, Zhen ; Dong, Chuan-Sheng ; Tan, Xi
Author_Institution :
Dept. of Microelectron., Fudan Univ., Shanghai, China
Abstract :
A successive approximation register analog-to-digital converter(SAR ADC) targeted for use in RSSI(received signal strength indicator) is presented. The measured signal-to-noise-and-distortion ratios(SNDR) of the ADC is 53.95 dB at 1MS/s sampling rate with power consumption of 147.6 μW from 1.2-V supply voltage, thus the resulting FOM is 0.437 pJ/conversion-step. The ADC is fabricated in a 0.13-μm technology.
Keywords :
analogue-digital conversion; distortion; low-power electronics; RSSI application; analog-to-digital converter; low power SAR ADC; received signal strength indicator; signal-to-noise-and-distortion ratios; successive approximation register; Approximation methods; Arrays; Capacitors; Control systems; Frequency measurement; Logic gates; Power demand;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667328
