Power-on surge current minimization in an SOI-SRAM-Based FPGA

A large and sudden current called surge current is always induced due to the momentary supply current through a low resistance path to ground when filed programmable gate array (FPGA) power on. This surge current will request the power supply of FPGA to source more current to meet this instantaneous demand or complicate the power management system of FPGA in order to succeed in powering up FPGA. Therefore, we describe and analyze the power-on surge current of FPGA in detail in this paper. According to the cause of power-on surge current, we modify the power-on sequence of FPGA, propose a novel SRAM cell embedded in the FPGA and add power routing pool to the FPGA, which have been implemented in an SRAM-Based FPGA, fabricated with a 0.5μm SOI CMOS process. The experimental results of full chip power-on indicate that the power-on surge current of FPGA has been significantly reduced compared with Xilinx Spartan and Spartan II family devices.