DocumentCode
1629200
Title
Design of an IPSec IP-Core for 10 Gigabit Ethernet Security Processor
Author
Wang, Li ; Niu, Yun ; Wu, Liji ; Zhang, Xiangmin
Author_Institution
Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China
fYear
2010
Firstpage
539
Lastpage
541
Abstract
Design of an IPSec (Internet Protocol Security) IP-Core for 10 Gigabit Ethernet Security Processor is presented in this paper. The highest data throughput of one IPSec IP-Core can achieve 1.5Gbps. With parallel 8 IP-Cores, this design can achieve 10Gbps data process and fulfill a Gigabit Ethernet Security Processor requirement. The low power dissipation is also used in the IP-Core to reduce power dissipation.
Keywords
Internet; computer network security; local area networks; multiprocessing systems; protocols; Ethernet security processor; IPSec IP-Core; Internet protocol security; power dissipation; Authentication; IP networks; Internet; Process control; Protocols; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location
Shanghai
Print_ISBN
978-1-4244-5797-7
Type
conf
DOI
10.1109/ICSICT.2010.5667343
Filename
5667343
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