Title :
An optimized tag sorting circuit in WFQ scheduler based on leading zero counting
Author :
Huang, Xiao-Ping ; Fan, Xiao-Ya ; Zhang, Sheng-Bing ; Zhang, Fan
Author_Institution :
Comput. Sch., Northwestern Polytech. Univ., Xian, China
Abstract :
The tag sorting circuit in Weighted Fair Queuing (WFQ) is crucial to the Quality of Service (QoS). In this paper, we present a kind of optimized hardware architecture for fast tag sorting, which consists of one-hot encoding and leading zero counting. The architecture is parallel and pipelining. It is implemented using FPGA technology. In comparison with the traditional comparator-tree-based architecture, it can improve the frequency by 15% and reduce the area by 22%.
Keywords :
comparators (circuits); counting circuits; field programmable gate arrays; pipeline processing; quality of service; queueing theory; sorting; FPGA technology; QoS; WFQ scheduler; comparator-tree-based architecture; fast tag sorting; hardware architecture; hot encoding; leading zero counting; optimized tag sorting circuit; pipelining; quality of service; weighted fair queuing; Computer architecture; Field programmable gate arrays; Hardware; Logic gates; Pipeline processing; Quality of service; Sorting;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667346
