DocumentCode
1629284
Title
Process monitoring oriented IC testing
Author
Maly, Wojciech ; Naik, Samir B.
Author_Institution
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear
1989
Firstpage
527
Lastpage
532
Abstract
The authors proposed the use of functional testing for the extraction of IC manufacturing defect characteristics. It is demonstrated, using an SRAM (static random-access memory) example, that such extraction is feasible if an appropriate methodology for the interpretation of testing results is applied. The methodology allows for the extraction of information about process disturbances and abnormalities causing IC malfunctions. In this methodology the Monte Carlo fault modeling technique, combined with circuit simulation, was applied to build a defect fault vocabulary. The simulation experiment conducted by using this methodology demonstrated that a spectrum of signatures can be created to represent process disturbances. It was also shown that such a spectrum of signatures can be sensitive enough to changes in the defect densities
Keywords
Monte Carlo methods; digital simulation; electronic engineering computing; fault location; integrated circuit testing; integrated memory circuits; production testing; random-access storage; IC malfunctions; IC testing; Monte Carlo fault modeling; SRAM; circuit simulation; defect densities; defect fault vocabulary; functional testing; integrated memory circuits; production testing; spectrum of signatures; static random-access memory; Circuit faults; Circuit simulation; Circuit testing; Data mining; Integrated circuit testing; Manufacturing; Monitoring; Monte Carlo methods; Random access memory; Vocabulary;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location
Washington, DC
Type
conf
DOI
10.1109/TEST.1989.82336
Filename
82336
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