Design and verification of logic block circuit in an SOI-based FPGA

A novel logic block circuit consisting of two multi-mode logic cells is proposed for the design of a tile-based FPGA fabricated with a 0.5μm SOI-CMOS logic process. Each logic cell contains two 3-LUTs. The proposed 3-LUT based logic cell circuit increases logic density by about 12% compared with a traditional 4-LUT implementation. The logic block can be used in two functional modes: LUT mode and Distributed RAM mode, the latter of which can be configured in two modes: Single-Port RAM and Dual-Port RAM. Comparing with the published data on the CLB in Xilinx Spartan FPGA, the maximum LUT logic propagation delay has about 20% improvement and the Distributed RAM average access time has about 21% improvement.