Fabrication of axially-doped silicon nanowire tunnel FETs and characterization of tunneling current

Recent interest in low-power electronics has sparked considerable interested in gate-controlled tunneling-based transistors (TFETs), which have demonstrated inverse subthreshold slopes (S) better than the MOSFET limit of 60 mV/dec. While the natural progression of these devices to nanoscale dimensions promises improved performance, there is a lack of experimental data regarding the physics of tunneling at reduced dimensions. Here we present a TFET fabricated from an individual axially-doped p⁺-n-n⁺ Si nanowire in a device layout that enables the study of tunneling physics as the wire dimensions are scaled to the 1D transport regime.