A novel vector/SIMD multiply-accumulate unit based on reconfigurable booth array

Author

Quan, Heng ; Xiao, Ruijin ; You, Kaidi ; Zeng, Xiaoyang ; Yu, Zhiyi

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2010

Firstpage

524

Lastpage

526

Abstract

This paper presents a 32-bit vector multiply-accumulate (MAC) architecture capable of supporting multiple precisions. The vector MAC can perform one 32÷32, one 32÷16, two 16÷16, four 8÷8 bit signed/unsigned multiply-accumulate using Booth encoding algorithm and Wallace tree compressing. A reconfigurable Booth encoding array is implemented using 8÷8 Booth unit as the basic element, and longer bit modes are obtained by combining these elements selectively. This MAC unit can also perform multiply between scalar and vector operands. 32-bit SIMD (Single Instruction Multiple Date) extended ISA (Instruction Set Architecture) and 3-stage pipeline are implemented for the MAC unit. The design is synthesized in 0.13um SMIC technology under worst case condition, and the critical path of MAC is 2.5ns.

Keywords

encoding; instruction sets; logic design; multiplying circuits; parallel processing; reconfigurable architectures; Booth encoding; SIMD multiply-accumulate unit; SMIC technology; Wallace tree compressing; critical path; instruction set architecture; size 0.13 mum; vector multiply-accumulate architecture; Arrays; Digital signal processing; Encoding; Multimedia communication; Pipelines; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5797-7

Type

conf

DOI

10.1109/ICSICT.2010.5667353

Filename

5667353