Performance measurement of a fully pipelined JPEG codec on emulation platform

This paper presents the design and performance measurement of the hardware JPEG codec on an ARM926EJS emulation base board. JPEG is one of the best compression algorithms for still images. It preserves the quality with high compression ratio. JPEG codec encodes and decodes coloured as well grey image formats. The design exploits the pipeline architecture for high throughput. Overall size of the codec is controlled by sharing the common resources between JPEG encoder and decoder. Hardware JPEG codec was synthesized for Xilinx^¿ Virtex II FPGA device on ARM926EJS emulation base board. The paper covers all the RTL modifications done for performance measurement. FPGA resource utilization is tabulated at post-synthesis and post-mapping stage. Real time performance measurement is done for encoder and decoder for colored and grey images.