Title :
UiMOR - UC Riverside Model Order Reduction Tool for post-layout wideband interconnect modeling
Author :
Tan, Sheldon X -D ; Wang, Hai ; Yan, Boyuan
Author_Institution :
Dept. of Electr. Eng., Univ. of California, Riverside, CA, USA
Abstract :
In this paper, we introduce a new model order reduction tool, UiMOR - UC Riverside Model Order Reduction Tool. UiMOR fills the gap between parasitic extraction and post-layout simulation to improve the efficiency of VLSI circuit validation. UiMOR is a stand-alone circuit complexity reduction tool. It can perform accurate reduction for wideband frequency range with negligible loss of accuracy and is well suited for analog/mixed-signal/memory designs. It also works well for traditional delay and noise calculations in digital circuits. It works seamlessly with the existing digital and analog design tools that use the standard SPICE format interface. We then present some numerical comparison results with an existing industry tool, Ultrasim. UiMOR is now available for free download from UC Riverside.
Keywords :
SPICE; VLSI; circuit complexity; integrated circuit interconnections; SPICE format interface; UC riverside model order reduction tool; UiMOR; VLSI circuit validation; parasitic extraction; post-layout simulation; post-layout wideband interconnect modeling; stand-alone circuit complexity reduction tool; Accuracy; Computational modeling; Design automation; Integrated circuit interconnections; Integrated circuit modeling; RLC circuits; SPICE;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667360
