Title :
TCAD modeling challenges for 22nm node and beyond
Author_Institution :
TCAD Div., Taiwan Semicond. Manuf. Co. (TSMC) Ltd., Hsinchu, Taiwan
Abstract :
According to 2009 ITRS roadmap, advances in process technologies, introduction of new materials, and adoption of new device architectures are expected to enable CMOS scaling to 22nm node and beyond. The added process complexity will likely to lead to increased process development time and cost. Predictive TCAD modeling can be invaluable to guide development direction, narrow down experimental conditions and reduce the length and number of learning cycles. Significant TCAD modeling challenges exist in comprehending new physics and developing efficient and effective methodologies. This review paper focuses on FEOL modeling and highlights major challenges in: USJ, stress and variability modeling. Existing TCAD capability gaps and model development needs are discussed.
Keywords :
CMOS integrated circuits; semiconductor device models; technology CAD (electronics); CMOS scaling; FEOL modeling; TCAD modeling; USJ; device architecture; size 22 nm; stress modeling; variability modeling; Integrated circuit modeling; Numerical models; Semiconductor device modeling; Semiconductor process modeling; Solid modeling; Stress; Three dimensional displays;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667363
