An area efficient architecture of resisting long echo channel estimation for DTMB system

This paper proposed a VLSI architecture of resisting long echo channel estimation which is based on the algorithm proposed in. FFT module reusing and clock gating are used in order to reduce the hardware complexity and power consumption. The synthesis results show that the area can be reduced to only 65.5% of architecture in which FFT modules are not be reused. And the power can also be reduced a lot (the Design Compiler result shows that the power of the scheme can reduced to 29.6% of that before optimization).