Title :
An area efficient architecture of resisting long echo channel estimation for DTMB system
Author :
Ge, Yunlong ; Chen, Xubin ; Zhou, Changsheng ; Chen, Yun ; Wang, Yizhi ; Zeng, Xiaoyang
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
This paper proposed a VLSI architecture of resisting long echo channel estimation which is based on the algorithm proposed in. FFT module reusing and clock gating are used in order to reduce the hardware complexity and power consumption. The synthesis results show that the area can be reduced to only 65.5% of architecture in which FFT modules are not be reused. And the power can also be reduced a lot (the Design Compiler result shows that the power of the scheme can reduced to 29.6% of that before optimization).
Keywords :
VLSI; channel estimation; digital television; DTMB system; FFT module; VLSI architecture; clock gating; design compiler; hardware complexity; long echo channel estimation; Broadcasting; Channel estimation; Clocks; Hardware; Random access memory; Timing; Very large scale integration; DTMB; VLSI; area efficient; channel estimation; long echo;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667364
