A robust multipurpose PLL with lock detector designed in a 0.35 μm CMOS technology

In this paper, the design of a phase locked loop (PLL) with an additional lock detector with multiple output is presented. The proposed PLL is optimized for 2.5 V supply voltage and 20 MHz input reference signal. The PLL circuit also has 3 outputs of 170 MHz, 10.625 MHz and 10 MHz frequency. A lock detector is included in the PLL design, which indicates the lock state by generating logic 1 at its output. The complete design occupies 274 × 345 μm².