Optimized hardware for polynomial digital predistortion system implementation

In this paper, a new formulation of the polynomial based digital predistortion (DPD) is proposed. This formulation reduces the amount of hardware resources (memory and logic) required for the implementation while maintaining adequate precision. Additionally, a calibration of the transceiver is addressed to minimize its distortions. An implementation of this technique is validated in a field programmable gate array (FPGA) environment when using the mixed-signal transceiver (MSDPD) evaluation board. The proposed system allowed a reduction of more than 20 dB in terms of ACPR and EVM.