Novel approach to design a testable conservative logic gate for QCA implementation

In the Low power Nanocomputing era, Reversible and Conservative logic gate design is emerging as an important area of research. In this paper, we present a Novel approach to design conservative logic gate (CLG) using 3×3 tile nanostructure, as reversible logic design research gets amplitude. On the other hand study of 3×3 tile make fruitful result as it have diverse application, mentioned in this paper. It is a Novel nanostructure that is applied here to implement CLG. The basic principle of CLG is Parity preserving in both input as well as output. Here we applied 3×3 orthogonal MV to implement the logic and Cross wire is implemented with the help of 3×3 Baseline tile. The main advantage of this design we achieve that the numbers of Layer required only one. It also been demonstrated that the proposed design offers less numbers of QCA cell as well as less area and less clocking zones then the existing counterparts. We also analyzed the logic synthesis using our proposed gate. Here, we also found an effective and promising result and excels all existing counterparts. We demonstrate the testability of proposed CLG by means of behavioral approach of both inputs and outputs.