SRAM power optimization with a novel circuit and architectural level technique

In this paper, an integrated 512KB SRAM architecture with low power circuit design is presented. An extra Z decoding circuit is introduced, which is combined with divided wordline/bitline scheme to reduce half-selected memory cells and thus dynamic power is decreased significantly. In circuit level, we utilize source biasing scheme to achieve leakage reduction and adopt an extra clamping diode in parallel with pull-down NMOS transistor to obtain data retention capability. Besides, power-gating method is proposed for wordline driver circuits. Simulation results on 55nm CMOS process indicates that leakage power and dynamic power can be saved by 66.7% and 27.9% respectively compared to conventional SRAM structure with performance penalty less than 3%.