Implementation of branch delay in Superscalar processors by reducing branch penalties

Branch prediction is crucial to maintaining high performance in modern superscalar processor. Today´s superscalar processors achieve high performance by executing multiple independent instructions in parallel. One of the most impedement to the performance of wide-issue superscalar processor is the presence of conditional branches. Conditional branches can occur as frequently as one in every 5 or 6 instructions, leading to heavy misprediction penalties in superscalar architectures. Ideal speed-up in superscalar processor is seldom achieved due to stalls and breaks in the execution stream. These interrupts are caused by data and control hazards which deteroits the superscalar processor performance. Branch target buffer (BTB) can reduces the performance penalty of branches in superscalar processor by predicting the path of the branch and caching information used by the branch. No stalls will be encountered if the branch entry is found in the BTB and prediction is correct. Otherwise, the penalty will be of at least `2´ cycles. This paper proposes an algorithm for superscalar processor based on changing the BTB structure to eliminate the misprediction penalty. It also highlights a problem in the previous BTB algorithm (nested branches problem) and proposes a solution to it.