DocumentCode :
1630310
Title :
Evaluation of test metrics: stuck-at, bridge coverage estimate and gate exhaustive
Author :
Guo, Ruifeng ; Mitra, Subhasish ; Amyeen, Enamul ; Lee, Jinkyu ; Sivaraj, Srihari ; Venkataraman, Srikanth
Author_Institution :
Intel Corp., Santa Clara, CA
fYear :
2006
Lastpage :
71
Abstract :
Production test data from more than 500,000 chips is analyzed to understand the correlation between the number of defective chips detected by a set of test patterns and the coverage values of these test patterns with respect to various test metrics. Experimental results show that the gate exhaustive metric has the highest correlation when compared to the stuck-at and the bridge coverage estimate metrics, especially for high coverage test patterns. More than 69% of all test patterns can be removed from the test set without reducing the number of detected chips - more than 99% of these patterns are required to obtain high stuck-at coverage. None of the test metrics are very effective in predicting which subset of a given set of test patterns can be removed from the test set without compromising test quality before the patterns are actually applied to manufactured ICs
Keywords :
bridge circuits; data analysis; integrated circuit testing; system-on-chip; bridge coverage estimate; defective chips; gate exhaustive; production test data analysis; stuck-at; test metrics evaluation; Automatic test pattern generation; Automatic testing; Bridges; Compaction; Manufacturing; Pattern analysis; Production; Silicon; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 2006. Proceedings. 24th IEEE
Conference_Location :
Berkeley, CA
Print_ISBN :
0-7695-2514-8
Type :
conf
DOI :
10.1109/VTS.2006.34
Filename :
1617564
Link To Document :
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