A high resolution FPGA-based TDC with nonlinearity calibration

This paper proposes multi-path delay line (MPDL) time-to-digital converter (TDC). Instead of traditional tapped delay line (TDL) TDC, the proposed MPDL-TDC can improve the linearity performance effectively. Implemented in a Xilinx XC5VLX110T-1FF1136 field-programmable gate array (FPGA) device, the proposed MPDL-TDC has 60 ps time resolution, and the ranges of differential non-linearity (DNL) and integral non-linearity (INL) are [-0.52,0.52] and [-0.79,1.06] least-significant-bit (LSB), respectively. Furthermore, 37.25 ps root-mean-square (RMS) is measured for the proposed MPDL-TDC inputting a constant delay source. Therefore, the proposed MPDL-TDC is recommended to implement in FPGA-based TDC achieving a high-resolution time and linearity performance.