A 250 MHz shared-resource VLSI test system with high pin count and memory test capability

Author

Kikuchi, Shuji ; Hayashi, Yoshihiko ; Matsumoto, Takashi ; Yoshino, Ryozou ; Takagi, Ryuichi

Author_Institution

Hitachi Ltd., Kanagawa, Japan

fYear

1989

Firstpage

558

Lastpage

566

Abstract

The authors describe a 250-MHz, 2048-pin, shared-resource VLSI test system which has timing accuracy up to 300 ps and a parallel algorithmic pattern generation system for embedded memory testing. A timing generation system which provides an effective deskewing scheme in a shared-resource tester is proposed. Parallel pattern generation for high-speed memory testing is introduced, and a conversion strategy for parallel programs is discussed

Keywords

VLSI; automatic test equipment; electronic engineering computing; integrated circuit testing; integrated memory circuits; parallel algorithms; 250 MHz; 300 ps; ATE; deskewing; embedded memory testing; high pin count; high-speed memory testing; parallel algorithmic pattern generation; parallel programs; shared-resource VLSI test; timing generation; Accuracy; Buffer storage; Circuit testing; Electronic equipment testing; Hardware; Logic testing; System testing; Test pattern generators; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1989. Proceedings. Meeting the Tests of Time., International

Conference_Location

Washington, DC

Type

conf

DOI

10.1109/TEST.1989.82340

Filename

82340

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1630380