Title :
Upper bounding fault coverage by structural analysis and signal monitoring
Author :
Agrawal, Vishwani D. ; Bose, Soumitra ; Gangaram, Vijay
Author_Institution :
Dept. of ECE, Auburn Univ., AL
Abstract :
A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, certain signal conditions are monitored during logic simulation. These signal conditions are specified by an analysis of dominators and signal reconvergences in the circuit graph. After simulation, a post-processing step identifies faults that cannot be detected by the sequence. For combinational IS GAS benchmarks, the runtime overhead for the algorithm is found to be around 30-40% over that of a logic simulator. Experimental data show a substantial reduction of error in statistical estimates obtained by a stuck-fault coverage estimator when corrected for faults found by this algorithm as guaranteed to be undetected by the given sequence. An effective application of this technique is demonstrated for scan-based test point selection in an industrial scenario where circuit size and vector length prohibit the use of fault simulation
Keywords :
circuit simulation; combinational circuits; fault simulation; logic simulation; logic testing; sequential circuits; circuit graph; combinational circuits; fault simulation; logic simulation; signal monitoring; structural analysis; stuck faults; upper bounding fault coverage; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Fault diagnosis; Logic; Monitoring; Signal analysis;
Conference_Titel :
VLSI Test Symposium, 2006. Proceedings. 24th IEEE
Conference_Location :
Berkeley, CA
Print_ISBN :
0-7695-2514-8
DOI :
10.1109/VTS.2006.89
