Title :
Minimal march test algorithm for detection of linked static faults in random access memories
Author :
Harutunyan, G. ; Vardanian, V.A. ; Zorian, Y.
Author_Institution :
Virage Logic, Yerevan
Abstract :
In this paper, a new notion of 2-composite static faults covering all unlinked and (realistic) linked static faults is introduced. We have introduced 120 new linked fault primitives missing in the paper by Hamdioui et al (IEEE TCAD 2004), thus extending the universe of linked fault primitives known before by 25%. A march test algorithm of length 23N (N - number of memory words) for detection of linked static faults in random access memories is proposed. It reduces the length of a previously known algorithm (Hamdioui et al., IEEE TCAD 2004) by 18N. We proved the proposed test is of minimum length
Keywords :
integrated circuit testing; random-access storage; 2-composite static faults; linked fault primitives; linked static faults detection; minimal march test algorithm; random access memories; Circuit faults; Circuit simulation; Circuit testing; DRAM chips; Fault detection; Logic; Random access memory; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 2006. Proceedings. 24th IEEE
Conference_Location :
Berkeley, CA
Print_ISBN :
0-7695-2514-8
DOI :
10.1109/VTS.2006.46
