CMOS NBTI degradation and recovery behaviors in a wide temperature range

Negative Bias Temperature (NBT) degradation in PMOS device with ultrathin SiON gate dielectric has been investigated at the temperature ranging from 218 K to 463 K. It is found that the degradation has different time-dependence behavior and activation energy above and below 268 K, evidencing two mechanisms in NBT degradation. One is related to interface state traps suggested in classic R-D model with neutral hydrogen atoms (H) as the diffusion species. The other is the hole trapping generation. The later dominates NBT degradation below 268 K. The possible hole trapping mechanism is proposed as inelastic hole tunneling and trapping into oxygen and nitrogen-related trap precursors under NBT stress.