On the implementation of an efficient multiplier logic for FPGA-based cryptographic applications

The efficiency of cryptographic algorithms when implemented in reconfigurable hardware is mainly determined by the fact of how the underlying finite field arithmetic operations are realized. Especially the field multiplication operation is crucial to the efficiency of a design, since it is the core operation of many cryptographic algorithms. This paper deals with the FPGA implementation of a Montgomery Multiplier architecture which operates on multiple words. The design scales up very easily and can be utilized as a unified architecture which can operate in different types of finite fields. The main focus of this ongoing research work is the conceptual design, development and implementation of a reconfigurable FPGA-based hardware security module.