Two management approaches of the split data cache in multiprocessor systems

As processor speed continues, the gap between the processor cycle and the memory subsystem cycle is expected to grow. One solution to this growing problem is to maximize the first level (LI) cache hit ratio, therefore the mean memory access time call decrease. Several studies have been made in order to manage more efficiently the LI data cache, both in uniprocessor and in multiprocessor systems. These studies seek two main objectives, to increase the LI hit ratio and to reduce the chip area occupied by these caches. In this work we present two new different approaches for increasing the LI hit ratio in multiprocessor systems and we compare with a conventional organization. Performance evaluation and hardware cost of these organizations are also calculated and compared with the cost incurred by the most common organization used