Title :
New robust 200mV sub-threshold full adders
Author :
Wang, Xu ; He, Weifeng ; Mao, Zhigang
Author_Institution :
Sch. of Microelectron., Shanghai Jiao Tong Univ., Shanghai, China
Abstract :
In this paper, two novel structures at 200mV 0.18um sub-threshold full adders are proposed for wireless sensor network nodes or medical electronics. They use three state gate to enhance the transition time and drivability of carry out signal. Simulation results show that the transition time of the proposed structure using three state gate is 60% of that of old structure using transmission gate. The proposed full adders are employed in an 8-bit ripple carry adder and the simulation results exhibit 20% power saving and 34% Power-Delay Product (PDP) saving compared to typical CMOS adder.
Keywords :
CMOS digital integrated circuits; adders; carry logic; low-power electronics; 8-bit ripple carry adder; CMOS adder; PDP saving; medical electronics; power-delay product saving; sub-threshold full adder; transmission gate; voltage 200 mV; wireless sensor network; Adders; CMOS integrated circuits; Delay; Logic gates; Partial discharges; Simulation; Transistors;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667416
