Architecture of the 2B1Q symbol receiver in the MC145472 ISDN U transceiver

Motorola and BNR are currently developing the MC145472, a single-chip implementation of an ISDN U reference point, 2B1Q transceiver which conforms to the T1E1 ANSI standard, T1.601. The authors describe the architecture of the portion of the chip that implements the symbol receiver function. The LMS pipe coprocessor and the MEC coprocessor are discussed. A typical execution sequence is also described. It is shown that the processors constituting the symbol receiver enable the U transceiver to recover the 2B1Q symbols and receive clock from the highly distorted receive signal stream. The implementation allows for high processing throughput and maximum flexibility while displacing minimum die area