A new Membrane PSOI High Voltage Device with a Buried P+ layer

A new Membrane PSOI High Voltage Device with a Buried P+ layer (MBP+ PSOI) is proposed. Breakdown voltage is only decided by lateral breakdown voltage because of the entire removing of silicon substrate under the drift region and breakdown voltage can be improved with increase of the length of the drift region. Introducing of P+ layer can effectively reduce specific on-resistance and silicon window results in alleviating significantly SHE. The simulation results show that breakdown voltage of MBP+ SOI is 734V and increases by 548V at L_d=37μm, t_s=4μm and t_I=1μm, in comparison with that of SOI LDMOS. In contrast to Camsei SOI, the maximal surface temperature for MBP+ PSOI decreases by 34K and specific on-resistance reduces by about 44.8%.