Test structure for electrical characterization of copper nanowire anisotropic conductive film (NW-ACF) for 3D stacking applications

Author

Jing Tao ; Mathewson, A. ; Razeeb, Kafil M.

Author_Institution

Microsyst. Center, Tyndall Nat. Inst., Cork, Ireland

fYear

2014

fDate

24-27 March 2014

Firstpage

165

Lastpage

169

Abstract

Copper nanowire arrays (~200 nm diameter) grown in porous polymer template is a potential low temperature interconnection technology compared to metal/metal or solder micro-bump interconnects for 3D chip stacking. To advance this technology, good understanding of material and process related electrical properties is required. In this paper, a stacked test chip module with copper daisy chain pattern, which is finished by ~1 μm indium bonding layer, has been designed to extract the resistance and capacitance data of the NW-ACF.

Keywords

copper; integrated circuit interconnections; nanowires; three-dimensional integrated circuits; 3D chip stacking; 3D stacking applications; NW-ACF; capacitance data; copper daisy chain pattern; copper nanowire anisotropic conductive film; copper nanowire arrays; electrical characterization; electrical properties; indium bonding layer; low temperature interconnection technology; metal-metal technology; porous polymer template; resistance data; solder microbump interconnects; stacked test chip module; test structure; Bonding; Capacitance; Electrical resistance measurement; Leakage currents; Resistance; Semiconductor device measurement; Three-dimensional displays; 3D chip stack; NW-ACF (Nanowire Anisotropic Conductive Film); capacitance; interconnection resistance; leakage current; thermocompression bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures (ICMTS), 2014 International Conference on

Conference_Location

Udine

ISSN

1071-9032

Print_ISBN

978-1-4799-2193-5

Type

conf

DOI

10.1109/ICMTS.2014.6841487

Filename

6841487