Title :
A flexible high performance 2-D discrete cosine transform IC
Author :
Matterne, L. ; Chong, D. ; Sweeney, B. Mc ; Woudsma, R.
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
Abstract :
The authors present an ASIC that is able to execute a two-dimensional discrete cosine transform (2D-DCT) algorithm and its inverse (2D-IDCT) at a maximum input sample rate of 13.5 MHz. It is demonstrated that a separable, orthogonal transform like the 2D-DCT can efficiently be mapped on a very long instruction word multiprocessor architecture, which may accommodate other algorithms. Some details and the test strategy are also elaborated
Keywords :
application specific integrated circuits; computerised picture processing; digital signal processing chips; parallel architectures; transforms; 13.5 MHz; ASIC; VLIW architecture; algorithm accommodation; efficient mapping; input sample rate; inverse 2D-DCT algorithm; orthogonal transform; test strategy; two-dimensional discrete cosine transform algorithm; very long instruction word multiprocessor architecture; Accuracy; Application specific integrated circuits; Clocks; Costs; Discrete cosine transforms; Frequency; Integrated circuit packaging; Laboratories; Switches; VLIW;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100428
