Effects of metal spacing and poly-silicon layers on pulsed-laser single event transient testing

Author

Jinshun Bi ; Chuanbin Zeng ; Linchun Gao ; Duoli Li ; Gang Liu ; Jiajun Luo ; Zhengsheng Han ; Zhengshen Han

Author_Institution

Inst. of Microelectron., Beijing, China

fYear

2014

fDate

24-27 March 2014

Firstpage

207

Lastpage

212

Abstract

This paper investigates the influence of metal spacing and poly-crystalline silicon gate and silicide technology on single event transients (SETs) occurring in pulsed laser irradiated test patterns based on 0.18 μm partially depleted silicon-on-insulator complementary-metal-oxide-semiconductor technology. Laser-induced transients were measured and analyzed in detail, including SET rise time, fall time, pulse width, pulse maximum, and collected charge. The quantitative dependence of the SET characteristics on metal spacing and silicide processing is reported. This information is useful for optimal design of test structures to evaluate soft errors in integrated circuits.

Keywords

CMOS integrated circuits; integrated circuit testing; radiation hardening (electronics); silicon-on-insulator; SET; Si; collected charge; fall time; integrated circuits; laser-induced transients; metal spacing; partially depleted silicon-on-insulator complementary-metal-oxide-semiconductor technology; poly-crystalline silicon gate; poly-silicon layers; pulse maximum; pulse width; pulsed laser irradiated test patterns; pulsed-laser single event transient testing; rise time; silicide technology; size 0.18 mum; soft errors; Lasers; Logic gates; Metals; Resistors; Silicides; Silicon; Transient analysis; charge collection; laser test; partially-depleted silicon-on-insulator; single event transient; soft errors;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures (ICMTS), 2014 International Conference on

Conference_Location

Udine

ISSN

1071-9032

Print_ISBN

978-1-4799-2193-5

Type

conf

DOI

10.1109/ICMTS.2014.6841494

Filename

6841494